Components of a computational system typically communicate with one another via electrical signals conveyed by a bus. Such signals conform to a communication protocol that allows the components to exchange data in at least one predetermined format. For example, data may be exchanged between a first and second component using a synchronous data communication protocol wherein the first component places or asserts data signals on a plurality of parallel bus data transmission connections or lines, for a predetermined time interval and the second component reads the data from the bus during this predetermined time interval. Typically, a fixed amount of data is transferred between the two given components using this protocol.
Alternatively, data may be exchanged between a first and a second component using an asynchronous data communication protocol. In an asynchronous protocol, instead of data signals being asserted on the bus by the first component for a predetermined time interval, the data signals are asserted (i.e., maintained) on bus data transmission lines by the first component until an appropriate acknowledge signal is obtained from the second component acknowledging the data transfer signals were received. As with the synchronous protocol, typically a constant amount of data is also transferred with an asynchronous protocol.
In yet a third communication protocol, known as high speed synchronous, a plurality of synchronized data transfers from a first component to a second component occur without intervening data transfer control operations. That is, sets of parallelly communicated data bits (e.g., one or more bytes) are asserted on the bus data transmission lines, one set after another in rapid succession. Thus, a varying and potentially large amount of data can be transferred efficiently since bus timing cycles are not used for intervening control signals.
Many computational buses presently in use support either a synchronous, an asynchronous or a high speed synchronous protocol. Further, some buses support both a synchronous and an asynchronous protocol. However, a greater degree of flexibility is desirable such that each of the above protocols is supported on a single bus. Without the flexibility to support each of the three protocols, computational system designers are restricted in selecting system components due to component protocol incompatibilities. Such inflexibility causes designers to shun cost-effective components that do not provide a protocol supported by the bus being used. In addition, since it is not uncommon for sophisticated components to support a high speed synchronous protocol and one of either a synchronous or an asynchronous protocol, if the bus does not support all three protocols, then system designers are prevented from using the full versatility of such sophisticated components. In particular, system designers are prevented from using a component supported protocol that more appropriately satisfies a particular situation when the protocol is not supported by the bus.
To further enhance system design flexibility, it is also desirable to be able to vary the size of data transfers between components attached to the bus. For example, some components receive and/or supply only data transfers corresponding to a byte while other components receive and/or supply data transfers having sizes, for example, of two or four bytes.
It would be therefore advantageous to have a bus for a computational system having both fewer protocol restrictions and fewer data transfer size restrictions. That is, such a bus ought to be capable of supporting the three above mentioned data protocols and in addition also capable of data transfers of various sizes.